A VLSI design concept for parallel iterative algorithms

Parallel algorithms for VLSI computer-aided design

Parallel algorithms for VLSI circuit extraction

Parallel processing has recently become an extremely attractive and cost effective way of achieving orders of magnitude performance improvements in VLSI CAD applications. In this paper, we propose parallel algorithms to speed up the VLSI circuit extraction task. Given a VLSI layout as input, the problem of circuit extraction consists of determining the circuit connectivity and estimating the va...

Parallel Algorithms for VLSI Layout Verification

Layout veriication determines whether the polygons that represent diierent mask layers in the chip conform to the technology speciications. Commercial layout verii-cation programs can take tens of hours to run in the attened representations for large designs. It is therefore desirable to run the DRC problem in parallel to reduce the runtimes. Also, the memory requirements of large chips are suc...

Mapping Irregular Parallel Algorithms in Vlsi Processor Arrays Mapping Irregular Parallel Algorithms in Vlsi Processor Arrays ?

The paper presents an overwiev of our recent research of parallel algorithm mapping. We consider the mapping of irregularly structured algorithms in VLSI processor arrays. Although architectural improvements may contribute to the mapping eeciency, the area of mapping techniques is a more likely source for improvements. Therefore, we discused the following topics: optimization of mappings with s...

Let's Design Algorithms for VLSI Systems